1. Background of the Invention
Flip chip technology is the fastest growing chip interconnect technology as it allows the largest numbers of I/Os (input/output) for the smallest footprint of the chip. This allows small packages including packages such as chip-scale packages.
Gruber et al. in their paper “Low-cost wafer bumping,” IBM Journal of Research and Development, IBM JRD 49-4/5 (http://www.research.ibm.com/jpournal/rd/494/gruber.html) (Aug. 16, 2005) describe flip-chip solder-bump interconnections as the face-down soldering of integrated circuit (IC) devices to chip carriers by means of conductive bumps on the chip bond pad. The use of this bump technology also extends to passive filters, detector arrays and MEMs devices. IBM introduced this technology in the early 1960's with the solid logic technology in the IBM System/360™. It extended interconnection capabilities beyond existing wire-bonding techniques, allowing the area array solder-bump configuration to extend over the entire surface of the chip (die) providing solder bumps for interconnection to a substrate by the C4 (controlled collapse chip connection) solder reflow process developed by IBM. This allowed for the highest possible I/O counts to meet the increasing demand for electrical functionality and reliability in IC technology.
The original wafer-bumping process of metal mask evaporation in which ball-limiting metallurgy (BLM) also known as under board metallization, or under mask metallization, or under mask-bump metallurgy (UBM) involve the evaporation onto a wafer surface of solder through mask openings in an area array fashion. The need for increased I/O density and count, and pressures to lower the cost of flip-chip interconnections have spurred the development of other wafer bumping techniques such as electroplating or stencil-printing/paste-screening (solder paste) bump processes. Some of the more newly developed bumping processes include transfer printing, solder jetting, and bumpless and conductive particle applications.
In its broader aspect, BLM, or UBM comprises the application of a metal coating to the die contact pads such as aluminum or copper contact pads, where the metal coating provides a surface that can adhere to solder. One process involves cleaning an aluminum terminal pad followed by activation to remove any aluminum oxide layer on the pad and applying a thin layer of zinc by means of a single or double zincate coating. By following this coating with an electroless Ni(P) plating process the zinc is replaced with nickel which forms a strong bond between the nickel and aluminum. Manufacturers use a similar process for a copper terminal pad with the exception that they clean the pad first with a dilute etchant, followed by activation with a palladium dispersion or solution and then apply the electroless Ni (P) film, or alternatively an electrolytic or sputtered Ni (V) film. Subsequent steps involve application of solder, e.g., solder “bumps” to the metal coating. Gruber et al. (supra) give a detailed explanation of all of the foregoing processes.
The so-called “solder bumps” provide a space between the chip and the substrate, usually filled in the last steps of the assembly process with a nonconductive “underfill” material that adhesively joins the entire surface of the chip or die to the substrate. The underfill not only blocks water or other contaminants from entering into the structure but also locks the chip or die to the substrate so that differences in thermal expansion do not breaker damage the electrical connections of the bumps.
Government regulations and customer needs have also impacted flip-chip interconnection technology requiring manufacturers to make a major transition from Pb/Sn to Pb-free solders and to produce larger wafers. Pb-free solder introduced new challenges such as the compatibility of the bumping process with a wide variety of these solders, each of which may require different processing conditions. Additionally, the transition from 200-mm to 300-mm wafers requires a bumping process that can readily accommodate this nearly 125% area increase with no negative effect on bumping yields and/or overall bump quality.
As a result, new solder-bumping technologies have developed that include some of the attributes of plating (extendibility to larger wafers and smaller bump size/pitch) and solder paste screening (flexibility of Pb-free alloy selection and low cost). One process comprises injection-molded solder (IMS) technology developed at IBM Research as an outgrowth of earlier work using solder for high performance thermal joints.
Industry nonetheless pressed for lower cost, higher quality bumping processes, and to this end IBM developed the C4NP (C4 new process, announced on Sep. 13, 2004) for IMS wafer bumping processes. Gruber et al. (supra) describe this process which basically involves processing a wafer and a solder mold simultaneously, but in separate processes that subsequently merge. Solder fills the mold in a prearranged pattern, after which the filled mold goes through an inspection step and alignment step with a wafer. Prior to alignment the wafer undergoes BLM deposition and patterning followed by inspection. After aligning mold and wafer the assembled components go through a reflow process to transfer solder to the wafer.
Other publications also describes flip chip manufacturing methods including inter alia “Injection Molded Soldering,” http//www.research.ibm.com/ims/; and “Flipchips.com Tutorials,” http//www.flipchips.com/tutorial01html; http//www.flipchips.com/tutorial02ahtml; http//www.flipchips.com/tutorial06html; http//www.flipchips.com/tutorial12html; http//www.flipchips.com/tutorial16html; http//www.flipchips.com/tutorial18html; http//www.flipchips.com/tutorial48html; and http//www.flipchips.com/tutorial55html.
The overview of flip chip technology shows its major advantage lies in utilizing the total chip area to make the I/O connections, whereas wire bonding uses only the chip periphery. A disadvantage of flip chip technology is that stresses that arise from the thermal mismatch between the silicon (chip) thermal expansion coefficient (CTE) and the CTE of the substrate are borne fully by the solder bumps (C4s) used to make the interconnect between chip and substrate. As noted, in order to ameliorate the stresses flip chip packages are usually underfilled, i.e., a resin is placed between the chip and the substrate and acts as encapsulant of the solder bumps and an adhesive between chip and substrate. The effect of such underfills is that the long-time reliability of underfilled flip chip packages is greatly enhanced compared to counterparts without an underfill.
Such resin underfill can be applied by capillary flow, using a so-called no-flow process or by wafer-level applied processes. There are several wafer-level applied underfill processes, among them the Wafer-level Underfill (WLUF) process (FIG. 1) which uses an over-bump wafer-applied resin, that is then b-staged, followed by dicing of the wafer to singulate chips and finally joining the chips with the WLUF layer to substrates. The WLUF process has been described by Buchwalter, Feger, Hougham, LaBianca, and Shobha, U.S. Pat. No. 6,919,420.
The WLUF process, however, has a few drawbacks such as the fact that the WLUF material must be applied to the full wafer before chip singulation. This requires wafer testing to identify bad chip sites and wafer-level burn in, if chip burn in is required before the chip is joined to the package. While these processes are possible, they require special tooling and thus add cost to the package.
Further, functioning and non-functioning (a.k.a. good and bad) chip sites are coated during the wafer-level underfill apply process. The materials and processing cost for the bad chip sites through singulation has to be added to the cost of making the good WLUF coated chips. This cost can be significant, if the yield of the wafer is low, i.e., at the beginning of a new program or for complex chips.
Further, application of the WLUF material to the wafer requires storage until the wafer can be diced and further storage until the WLUF coated chips can be joined to the package. This requires stability of wafer-applied WLUF material for up to 6 months and may require storage of such wafers under nitrogen or other special conditions.
The WLUF layer may also obscure the C4 pattern and/or other alignment marks making it difficult to align WLUF coated, diced chips to the substrate before joining. The WLUF in this regard may contain high pigment or filler loading in order to ameliorate the difference in the coefficient of thermal expansion (CTE) of the semiconductor chip and the circuit board joined to it but this has other consequences. Increased pigment or filler loading further opacifies the WLUF making it difficult to ascertain alignment features or markings on the board and/or chip.
While these obstacles can be overcome as described by Feger et al. supra and U.S. Pat. No. 6,919,420, it would be of great advantage, if a process could be developed that could be applied to a singulated chip prior to joining. This would be of particular advantage for multi-chip modules and CSP (chip-size package) applications.
2. Related Art
The following references comprise related art teachings:    “Acid-cleavable Acetal and Ketal Based Epoxy Oligomers,” S. Buchwalter, C. Feger, G. Hougham, N. LaBianca, and H. Shobha, U.S. Pat. No. 6,919,420.    “Bilayer Wafer-Level Underfill,” S. L. Buchwalter, D. Danovitch, F. E. Doany, P. A. Gruber, R. Iyengar, N. C. LaBianca, U.S. Pat. No. 6,924,171.    “A Wafer-level Underfill process for Flip-chip Packaging,” C. Feger, N. C. LaBianca, G. Hougham, H. K. Shobha, and S. L. Buchwalter, Proc. IMAPS Flip. Chip Tech. 2003 (Feger et al.)    R. Mahidhara, “Comparing Chip-Scale Packaging to Direct Chip Attach,” ChipScale, May-June 1999    L. Crane, D. Gamota, R. W. Johnson, and P Neathway, “Making Direct Chip Attach Transparent to Surface Mount Technology,” ChipScale, September-October, 1999 B. Ma, E. Zhang, S. H. Hong, Q. Tong and A. Savoca, “Material Challenges for Wafer Level Packaging”, Proc. Int. Symp. on Adv. Packag. Materials Processes, Properties and Interfaces P. 68, 2000.
The present invention provides such processes that address these needs to not only provide advantages over the related art, but also to substantially obviate one or more of the foregoing and other limitations and disadvantages of the related art. The written description, claims, abstract of the disclosure, and the drawings, that follow set forth various features, objectives and advantages of the invention and how they may be realized and obtained. They will also become apparent by practicing the invention.